The present invention generally relates to semiconductor devices and more particularly to a compound semiconductor field effect transistor having a diffusion region formed by an ion implantation of a dopant element.
Compound field effect transistors such as HFET (hetetostructure FET) or MESFET provide a very fast operational speed not attainable by conventional Si devices due to the characteristic band structure of the compound semiconductor material used for the device. Thus, compound semiconductor field effect transistors are used extensively for high speed devices for high frequency applications as well as for high speed processors.
In order to increase the operational speed of the device further, it is necessary to reduce the device size as much as possible. In relation to the stringent demand for such a device miniaturization, the self-alignment process developed for the fabrication of silicon devices, is used also in the fabrication of compound semiconductor field effect transistors. In the self-alignment process, source and drain regions are formed in a device substrate by introducing dopant elements thereto while using a gate electrode provided on the substrate as a mask. Since the gate electrode itself is used for the mask, an ideal mask alignment is achieved, even when the device size, such as the gate length, is minimized.
After such a process of ion implantation, a thermal annealing process is conducted for activating the dopant elements thus introduced such that the dopant elements occupy a proper site in the compound semiconductor crystal that forms the active part of the device. On the other hand, such a thermal annealing process tends to induce a diffusion of such dopant elements, while the diffusion of the dopant elements in turn may cause a modification of the distribution profile of the dopant elements in the device.
When the device is an extremely miniaturized one, it should be noted that such a modification of the element distribution profile may induce a corresponding modification of the diffusion region that may result in a modification of the operational characteristics of the device. When the source and drain regions cause a contact, for example, the transistor no longer operates properly.
FIG. 1 shows an example of a conventional compound semiconductor field effect transistor.
Referring to FIG. 1, the field effect transistor is constructed upon a substrate 21 carrying a gate electrode on an upper major surface thereof in correspondence to a channel region that is defined in the substrate 21, wherein the substrate 21 further includes a source region 23 and a drain region 24 at both sides of the channel region. Further, a source electrode 25 and a drain electrode 26 are provided respectively on the source and drain regions 23 and 24.
It should be noted that the structure of FIG. 1 is formed first by providing the gate electrode 22 on the upper major surface of the substrate 21, followed by an ion implantation process of the dopant elements into the substrate 21 while using the gate electrode 22 as a mask. After thermal annealing process to activate the dopant elements, the source and drain regions 23 and 24 are formed as indicated in FIG. 1.
In such a thermal annealing process, it should be noted that the dopant atoms may cause a diffusion and invade into the channel region immediately below the gate electrode 22. When such a diffusion of the dopant element occurs, the leak current of the device increases inevitably even when the device is turned off, and the device characteristic is deteriorated substantially.
In order to avoid such a problem of leak current, it is practiced, in the Si devices, to provide a side wall insulation such that the source and drain regions are separated from each other with a sufficient distance as indicated in FIG. 2.
Referring to FIG. 2, the semiconductor device is constructed upon a substrate 31 that carries a gate electrode 32 on an upper major surface thereof, wherein the gate electrode 32 in turn carries a pair of side wall insulation covers 33 at both lateral side walls thereof, such that the gate electrode 32 and the both side wall insulations covers 33 act together as a self-aligned mask when conducting an ion implantation into the substrate 31 to form source and drain regions 34 and 35 therein. As usual, source and drain electrodes 36 and 37 are provided on the source and drain regions 34 and 35 respectively, after a thermal annealing process to activate the dopant element in the source and drain regions 34 and 35. In the structure of FIG. 2, it should be noted that the problem of the source and drain regions 34 and 35 approaching excessively or even overlapping with each other, is effectively eliminated due to the increased separation between the source and drain regions 34 and 35.
While the structure of FIG. 2 may be effective for eliminating the foregoing problem of the source and drain regions 34 and 35 contacting with each other, such a structure has an obvious and inevitable drawback of increased gate length and hence a reduced operational speed of the device. In other words, the device of FIG. 2 eliminates the leak current by sacrificing the operational performance of the device. Conventionally, there has been no effective structure nor a fabrication process thereof to achieve a high integration density for a compound field effect transistor integrated circuit while simultaneously eliminating the diffusion of the dopant element into the channel region of the device.